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Memory centric hardware prefetching in multi-core processors

  • Beihang University
  • Beijing Simulation Center

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Hardware prefetching is widely employed in modern processors. It has been proved that prefetching can significantly improve application’s performance unless it exhibits sparse locality. Nevertheless, prefetching may result in performance degradation in CMP systems as it issues many off-chip memory requests. In this paper, we propose MCPref, a prefetching mechanism that is sensitive to the load of memory bus. Unlike traditional prefetching mechanism, MCPref opens when memory bus is starve and halts when memory bus is busy. Simulation results show that our non-feedback prefetcher design is effective in the scenario of multi-core architecture.

Original languageEnglish
Title of host publicationTrustworthy Computing and Services - International Conference, ISCTCS 2014, Revised Selected Papers
EditorsYueming Lu, Xu Wu, Xi Zhang, Yueming Lu, Xu Wu, Xi Zhang, Xu Wu
PublisherSpringer Verlag
Pages311-321
Number of pages11
ISBN (Print)9783662474006
DOIs
StatePublished - 2015
EventInternational Standard Conference on Trustworthy Computing and Services, ISCTCS 2014 - Beijing, China
Duration: 28 Nov 201429 Nov 2014

Publication series

NameCommunications in Computer and Information Science
Volume520
ISSN (Print)1865-0929

Conference

ConferenceInternational Standard Conference on Trustworthy Computing and Services, ISCTCS 2014
Country/TerritoryChina
CityBeijing
Period28/11/1429/11/14

Keywords

  • Hardware prefetching
  • Memory scheduling
  • Multi-core

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