Low power magnetic flip-flop based on checkpointing and self-enable mechanism

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep submicron CMOS technology. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Torque Transfer MRAM (STT-MRAM) is considered the most promising NVM technology to address this issue thanks to its fast speed, low power, and infinite endurance. In this paper, we present a new design of magnetic flip-flop (MFF) based on STT-MRAM. By integrating multi-context data checkpointing and self-enable switching mechanisms, its overall power can be lowered further than conventional structures. We performed hybrid simulations to validate its functional behaviors and evaluate its performance by using an accurate STT-MRAM spice model and an industrial CMOS 40 nm design kit.

Original languageEnglish
Title of host publication2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
DOIs
StatePublished - 2013
Externally publishedYes
Event2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013 - Paris, France
Duration: 16 Jun 201319 Jun 2013

Publication series

Name2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

Conference

Conference2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
Country/TerritoryFrance
CityParis
Period16/06/1319/06/13

Keywords

  • Checkpointing
  • Flip-Flop
  • Low power
  • Non-volatile
  • Register
  • Rollback
  • STT-MRAM
  • Stochastic switching

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