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Low error-floor majority-logic decoding based algorithm for non-binary LDPC codes

  • Beihang University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The traditional majority-logic decoding (MLgD) based algorithms suffer error-floors for decoding non-binary LDPC codes with small column weights. This paper presents a bit-reliability based MLgD (BRB-MLgD) algorithm with low error-floors for non-binary LDPC codes. The proposed algorithm is carried out based on the binary representations of non-binary symbols. The reliability update along each edge of the Tanner graph of a non-binary LDPC code is in terms of bits rather than symbols. Thus, its computational complexity and memory consumption are less than those of the existing MLgD based algorithms. Simulation results indicate that the proposed algorithm can significantly reduce error-floors with small performance degradation in the waterfall region.

Original languageEnglish
Title of host publication2015 IEEE International Conference on Communications, ICC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages4072-4076
Number of pages5
ISBN (Electronic)9781467364324
DOIs
StatePublished - 9 Sep 2015
EventIEEE International Conference on Communications, ICC 2015 - London, United Kingdom
Duration: 8 Jun 201512 Jun 2015

Publication series

NameIEEE International Conference on Communications
Volume2015-September
ISSN (Print)1550-3607

Conference

ConferenceIEEE International Conference on Communications, ICC 2015
Country/TerritoryUnited Kingdom
CityLondon
Period8/06/1512/06/15

Keywords

  • bit-reliability
  • error-floor
  • majority-logic decoding
  • Non-binary LDPC codes

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