TY - GEN
T1 - LLP-ECCA
T2 - 8th IEEE International Test Conference in Asia, ITC-Asia 2024
AU - Huang, Yicheng
AU - Wang, Xueyan
AU - Dai, Tianao
AU - Yang, Jianlei
AU - Lu, Zhaojun
AU - Jia, Xiaotao
AU - Qu, Gang
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Elliptic curve cryptography (ECC) plays a pivotal role in safeguarding data integrity and authentication in contemporary communication contexts, particularly within the domain of Intelligent Transport Systems (ITS). In the realm of ITS, vehicles communicate via the V2X (vehicle-to-everything) protocol, necessitating low-latency responses and minimal power consumption. Given the evolving nature of V2X protocol standards across the globe, programmability becomes a rigid requirement. However, existing strategies cannot meet all these vehicular equipment demands. This paper introduces a novel framework tailored for ECC acceleration to address the issues. Specifically, we propose the design of an Application Specific Instruction Set Processor (ASIP), augmented by pipeline and dual-issue techniques. Furthermore, the envisioned ASIP integrates a hybrid control framework founded on Finite State Machines (FSM), facilitating agile and effective management. Notably, a general GF(p256) Barrett modular multiplier is specially devised to optimize latency and area utilization. Experimental results on Xilinx Kintex Ultrscale+ FPGA demonstrate that the proposed ECC accelerator generates a signature within 131us and verifies a message within 181us, and the performance meets the requirements of today's V2X standard.
AB - Elliptic curve cryptography (ECC) plays a pivotal role in safeguarding data integrity and authentication in contemporary communication contexts, particularly within the domain of Intelligent Transport Systems (ITS). In the realm of ITS, vehicles communicate via the V2X (vehicle-to-everything) protocol, necessitating low-latency responses and minimal power consumption. Given the evolving nature of V2X protocol standards across the globe, programmability becomes a rigid requirement. However, existing strategies cannot meet all these vehicular equipment demands. This paper introduces a novel framework tailored for ECC acceleration to address the issues. Specifically, we propose the design of an Application Specific Instruction Set Processor (ASIP), augmented by pipeline and dual-issue techniques. Furthermore, the envisioned ASIP integrates a hybrid control framework founded on Finite State Machines (FSM), facilitating agile and effective management. Notably, a general GF(p256) Barrett modular multiplier is specially devised to optimize latency and area utilization. Experimental results on Xilinx Kintex Ultrscale+ FPGA demonstrate that the proposed ECC accelerator generates a signature within 131us and verifies a message within 181us, and the performance meets the requirements of today's V2X standard.
KW - Elliptic Curve Cryptography (ECC)
KW - Hardware Acceleration
KW - Programmable
KW - V2X
UR - https://www.scopus.com/pages/publications/85204788655
U2 - 10.1109/ITC-Asia62534.2024.10661323
DO - 10.1109/ITC-Asia62534.2024.10661323
M3 - 会议稿件
AN - SCOPUS:85204788655
T3 - Proceedings - ITC-Asia 2024: 8th IEEE International Test Conference in Asia
BT - Proceedings - ITC-Asia 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 18 August 2024 through 20 August 2024
ER -