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Lessons from experimental methodology of Cache hierarchy changes with the memory technology

  • Beihang University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Caching is an important technique to improve computer system performance by storing the most recently used data and instructions for main memory. Cache is widely used in modern computer systems and will continue to be an irreplaceable unit to narrow the speed gap between processor and main memory. With the increasing capacity of main memory and the number of processor cores, the cache technology has great development. In this paper, we have some lessons of cache hierarchy changes with the memory technology from experimental methodology. We design a serial of experiments and try to answer some questions about cache designs. Our experiments results indicate that more levels of cache does not necessarily means better performance for all benchmarks, that last level cache miss rate has no direct connection with the system performance, that the average performance of exclusive cache hierarchy is more effective than that of inclusive cache.

Original languageEnglish
Title of host publicationProceedings - 17th IEEE International Conference on Computational Science and Engineering, CSE 2014, Jointly with 13th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2014, 13th International Symposium on Pervasive Systems, Algorithms, and Networks, I-SPAN 2014 and 8th International Conference on Frontier of Computer Science and Technology, FCST 2014
EditorsXingang Liu, Didier El Baz, Ching-Hsien Hsu, Kai Kang, Weifeng Chen
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1953-1959
Number of pages7
ISBN (Electronic)9781479979813
DOIs
StatePublished - 26 Jan 2015
Event17th IEEE International Conference on Computational Science and Engineering, CSE 2014 - Jointly with 13th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2014, 13th International Symposium on Pervasive Systems, Algorithms, and Networks, I-SPAN 2014 and 8th International Conference on Frontier of Computer Science and Technology, FCST 2014 - Chengdu, China
Duration: 19 Dec 201421 Dec 2014

Publication series

NameProceedings - 17th IEEE International Conference on Computational Science and Engineering, CSE 2014, Jointly with 13th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2014, 13th International Symposium on Pervasive Systems, Algorithms, and Networks, I-SPAN 2014 and 8th International Conference on Frontier of Computer Science and Technology, FCST 2014

Conference

Conference17th IEEE International Conference on Computational Science and Engineering, CSE 2014 - Jointly with 13th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2014, 13th International Symposium on Pervasive Systems, Algorithms, and Networks, I-SPAN 2014 and 8th International Conference on Frontier of Computer Science and Technology, FCST 2014
Country/TerritoryChina
CityChengdu
Period19/12/1421/12/14

Keywords

  • Cache memory
  • Cache miss rate
  • Exclusive cache
  • Last level cache
  • Multi-level cache

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