Implementation of 32 k points ultra high speed FFT processor based on FPGA devices

An ultra high speed 32 k point pipelined fast Fourier transform (FFT) processor was designed with FPGA (field programmable gate arrays) implementation. The processor can operate at 125 MHz and is able to handle a continuous input complex data stream of 1 Giga-samples per second. The FFT processor is based on MDF (multi-path delay feedback) structure which combines the features of the SDF (single-path delay feedback) and MDC (multi-path delay commutator) architectures. The memory cost of the processor was decreased compared with the MDC architectures while the speed is higher than the SDF architectures. The algorithm and design model for the processor was established and the three modules of the processor according to the design model were optimized to decrease resource cost. The design was implemented with the Xilinx ISE development tool using VHDL and was verified with the FPGA place and router results.