Abstract
This letter presents a graphics processing unit (GPU)-based non-binary low density parity check multi-codeword decoder with both kernel execution and data transfer optimizations. A novel multi-codeword data structure and its corresponding parallelism are proposed to boost the compute unified device architecture kernel execution. Moreover, practical methods of hiding the data transfer latency are presented to improve data transfer efficiency. Experimental results demonstrate that the throughput speedups achieved by the proposed decoder range from 3.12 × to 185 × over various Galois fields compared with the existing works on GPU.
| Original language | English |
|---|---|
| Pages (from-to) | 486-489 |
| Number of pages | 4 |
| Journal | IEEE Communications Letters |
| Volume | 22 |
| Issue number | 3 |
| DOIs | |
| State | Published - Mar 2018 |
Keywords
- CUDA
- GPU
- Non-binary LDPC
- multi-codeword
- parallel decoding
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