Skip to main navigation Skip to search Skip to main content

High-speed data transmission system design and implementation based on FPGA

  • Bei Yan*
  • , Yuefeng Sun
  • *Corresponding author for this work
  • Beihang University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Aimed at the non-standard Flash memory composed of 8 K9KAG08U0M Flash chips of Samsung Company, the paper introduces a high-speed data transfer interface with FPGA (Field Programmable Gate Array) as the main controller. With the synchronous DMA (Direct Memory Access) mode of USB2.0, the system implements the management, reading and transmission of the data in the memory. The design of the system proves in practice that the effective transmission speed reaches 30MB/s and in just 15 minutes, all of the data in the 16.5G bytes non-standard memory can be downloaded to the hard disk of the computer.

Original languageEnglish
Title of host publicationProceedings - 2009 International Conference on Information Engineering and Computer Science, ICIECS 2009
DOIs
StatePublished - 2009
Event2009 International Conference on Information Engineering and Computer Science, ICIECS 2009 - Wuhan, China
Duration: 19 Dec 200920 Dec 2009

Publication series

NameProceedings - 2009 International Conference on Information Engineering and Computer Science, ICIECS 2009

Conference

Conference2009 International Conference on Information Engineering and Computer Science, ICIECS 2009
Country/TerritoryChina
CityWuhan
Period19/12/0920/12/09

Keywords

  • FLASH memory
  • FPGA
  • USB2.0

Fingerprint

Dive into the research topics of 'High-speed data transmission system design and implementation based on FPGA'. Together they form a unique fingerprint.

Cite this