High-quality GaAs/InSb core–shell nanowires grown by molecular-beam epitaxy

High-quality GaAs/InSb core–shell nanowires have garnered significant research interest owing to the exceptional properties of InSb, including its high electron mobility, strong spin–orbit coupling, and large g-factor, which are pivotal for advanced electronics and quantum technologies. Concurrently, GaAs/InSb core–shell nanowires have been extensively investigated due to their potential in realizing topological insulators and enabling dissipationless edge state transport, characteristics analogous to those sought in InAs/GaSb systems. However, the substantial lattice mismatch (∼14.6%) between GaAs and InSb poses considerable challenges in achieving high-quality heteroepitaxial shells. Detailed investigations into the growth, microstructure, and strain distribution within such systems remain limited. Here, we demonstrate the successful growth of high-quality GaAs/InSb core–shell nanowires via molecular-beam epitaxy, utilizing self-catalyzed pure zinc blende GaAs nanowire cores. Through systematic optimization, we identified that an InSb shell growth temperature of 390 °C and an Sb/In beam equivalent pressure ratio of 4.36 are crucial for obtaining smooth, continuous shells with uniform thickness. Advanced transmission electron microscopy analysis confirmed the epitaxial zinc-blende structures of both the core and shell, revealing a dislocation density of approximately 50 μm⁻¹ in the InSb shell, notwithstanding the lattice mismatch. Cross-sectional strain mapping, conducted via geometric phase analysis, unveiled a ∼15% compressive strain at the GaAs/InSb interface, along with complex residual strain within the shell, attributed to the hexagonal nanowire geometry. Field-effect transistors fabricated with back-gated configurations exhibited n-type conduction, with a room-temperature carrier mobility of 50 cm²⋅V⁻¹⋅s⁻¹ and Ohmic behavior. Our work provides useful insights for the growth and optimization of other highly mismatched core–shell nanowires, thereby facilitating their integration into complex device architectures.