Hierarchical Placement Algorithm for Analog Circuit With Polygonal Modules

With the increasing application of analog circuits, manual layout processes become time-consuming. Existing research on automatic placement primarily applies to rectangular modules, and it is challenging to simultaneously meet the requirements of speed, compactness, and high performance. This work presents a hierarchical placement algorithm for analog circuit, satisfying various constraints at the device level and distinguishing critical signal path modules from others at a higher level. To minimize the area and the Half Perimeter Wire length (HPWL), while considering the signal path penalty for critical hierarchies, a polygon edges searching method is proposed, which specifically supports polygons and rectangles. The experimental results demonstrate that the automatic placement achieves comparable simulation performance to the manual one, reflecting the swiftness and effectiveness of the proposed method.