HARS: A high-performance reliable routing scheme for 3D NoCs

Jun Zhou; Huawei Li; Yuntan Fang; Tiancheng Wang; Yuanqing Cheng; Xiaowei Li

doi:10.1109/ISVLSI.2014.56

HARS: A high-performance reliable routing scheme for 3D NoCs

Jun Zhou^*
, Huawei Li
, Yuntan Fang
, Tiancheng Wang
, Yuanqing Cheng
, Xiaowei Li

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

CAS - Institute of Computing Technology
University of Chinese Academy of Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

The poor yield of current available processes for Through-Silicon Via (TSV) fabrication leads to serious influence on the robustness of the vertical communications in 3D NoCs. The fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of 2D NoCs. In this paper, we propose a high-performance reliable routing scheme HARS, which is deadlock-free by obeying a mid-node-searching method raised for 3D Mesh NoCs without requiring any Virtual Channels (VCs). In HARS, we adopt DyADM routing, extending the classical 2D routing algorithm DyAD to 3D scenario in presence of permanent faults on the vertical links. HARS is able to support both one-fault and multi-fault models. The experimental results show that HARS has better performance, improved reliability and lower overhead compared to the state-of-the-art reliable routing schemes.

Original language	English
Title of host publication	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Publisher	IEEE Computer Society
Pages	392-397
Number of pages	6
ISBN (Electronic)	9781479937639
DOIs	https://doi.org/10.1109/ISVLSI.2014.56
State	Published - 18 Sep 2014
Event	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States Duration: 9 Jul 2014 → 11 Jul 2014

Conference

Conference	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
Country/Territory	United States
City	Tampa
Period	9/07/14 → 11/07/14

Keywords

3D Mesh
Networks-on-chip
fault-tolerance
reliability
routing scheme

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10.1109/ISVLSI.2014.56

Cite this

@inproceedings{51ad75d80e6c42049d2eb49c5e14afd0,

title = "HARS: A high-performance reliable routing scheme for 3D NoCs",

abstract = "The poor yield of current available processes for Through-Silicon Via (TSV) fabrication leads to serious influence on the robustness of the vertical communications in 3D NoCs. The fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of 2D NoCs. In this paper, we propose a high-performance reliable routing scheme HARS, which is deadlock-free by obeying a mid-node-searching method raised for 3D Mesh NoCs without requiring any Virtual Channels (VCs). In HARS, we adopt DyADM routing, extending the classical 2D routing algorithm DyAD to 3D scenario in presence of permanent faults on the vertical links. HARS is able to support both one-fault and multi-fault models. The experimental results show that HARS has better performance, improved reliability and lower overhead compared to the state-of-the-art reliable routing schemes.",

keywords = "3D Mesh, Networks-on-chip, fault-tolerance, reliability, routing scheme",

author = "Jun Zhou and Huawei Li and Yuntan Fang and Tiancheng Wang and Yuanqing Cheng and Xiaowei Li",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 ; Conference date: 09-07-2014 Through 11-07-2014",

year = "2014",

month = sep,

day = "18",

doi = "10.1109/ISVLSI.2014.56",

language = "英语",

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booktitle = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

publisher = "IEEE Computer Society",

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Zhou, J, Li, H, Fang, Y, Wang, T, Cheng, Y & Li, X 2014, HARS: A high-performance reliable routing scheme for 3D NoCs. in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI., 6903395, IEEE Computer Society, pp. 392-397, 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, United States, 9/07/14. https://doi.org/10.1109/ISVLSI.2014.56

TY - GEN

T1 - HARS

T2 - 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014

AU - Zhou, Jun

AU - Li, Huawei

AU - Fang, Yuntan

AU - Wang, Tiancheng

AU - Cheng, Yuanqing

AU - Li, Xiaowei

PY - 2014/9/18

Y1 - 2014/9/18

N2 - The poor yield of current available processes for Through-Silicon Via (TSV) fabrication leads to serious influence on the robustness of the vertical communications in 3D NoCs. The fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of 2D NoCs. In this paper, we propose a high-performance reliable routing scheme HARS, which is deadlock-free by obeying a mid-node-searching method raised for 3D Mesh NoCs without requiring any Virtual Channels (VCs). In HARS, we adopt DyADM routing, extending the classical 2D routing algorithm DyAD to 3D scenario in presence of permanent faults on the vertical links. HARS is able to support both one-fault and multi-fault models. The experimental results show that HARS has better performance, improved reliability and lower overhead compared to the state-of-the-art reliable routing schemes.

AB - The poor yield of current available processes for Through-Silicon Via (TSV) fabrication leads to serious influence on the robustness of the vertical communications in 3D NoCs. The fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of 2D NoCs. In this paper, we propose a high-performance reliable routing scheme HARS, which is deadlock-free by obeying a mid-node-searching method raised for 3D Mesh NoCs without requiring any Virtual Channels (VCs). In HARS, we adopt DyADM routing, extending the classical 2D routing algorithm DyAD to 3D scenario in presence of permanent faults on the vertical links. HARS is able to support both one-fault and multi-fault models. The experimental results show that HARS has better performance, improved reliability and lower overhead compared to the state-of-the-art reliable routing schemes.

KW - 3D Mesh

KW - Networks-on-chip

KW - fault-tolerance

KW - reliability

KW - routing scheme

UR - https://www.scopus.com/pages/publications/84908206949

U2 - 10.1109/ISVLSI.2014.56

DO - 10.1109/ISVLSI.2014.56

M3 - 会议稿件

AN - SCOPUS:84908206949

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EP - 397

BT - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

PB - IEEE Computer Society

Y2 - 9 July 2014 through 11 July 2014

ER -

HARS: A high-performance reliable routing scheme for 3D NoCs

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Keywords

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