Hardware design and algorithm optimization of video encoder based on DSP and FPGA techniques

With the development of video encoding techniques, video compression algorithms become more complicated. A real-time high resolution video encoder cannot be implemented with a single CPU or digital signal processor (DSP). A MPEG-4 video encoder is designed and implemented based on coordinated DSP and field programmable gate array (FPGA) techniques. The FPGA module takes the tasks of video acquisition, YUV separation and data I/O functions, while the DSP is dedicated for video compression. The data flow scheme of the MPEG-4 video compression is optimized by utilizing the DSP on-chip memory. A macro block (MB) type judging algorithm is proposed based on MB space complexity. It reduces effectively the computational complexity of the video compression. The experimental results indicate that the MPEG-4 video encoder implementation can encode 39.2 f/s in common intermediate format (CIF) resolution.