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Hardening techniques for MRAM-based non-volatile storage cells and logic

  • Y. Lakys*
  • , W. S. Zhao
  • , J. O. Klein
  • , C. Chappert
  • *Corresponding author for this work
  • Université Paris-Saclay
  • CNRS

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Magnetic RAM (MRAM) is considered as a promising non-volatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction "up" and "down" of electrons instead of positive and negative charge. However, MRAM-based non-volatile storage cells and logic circuits are vulnerable to Single Event Effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are presented in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on Configurable Logic Block to mitigate SET on data paths. By using 65nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness.

Original languageEnglish
Title of host publicationRADECS 2011 - 12th European Conference on Radiation and Its Effects on Component and Systems, Conference Proceedings
Pages669-674
Number of pages6
DOIs
StatePublished - 2011
Externally publishedYes
Event12th European Conference on Radiation and Its Effects on Component and Systems, RADECS 2011 - Sevilla, Spain
Duration: 19 Sep 201123 Sep 2011

Publication series

NameProceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

Conference

Conference12th European Conference on Radiation and Its Effects on Component and Systems, RADECS 2011
Country/TerritorySpain
CitySevilla
Period19/09/1123/09/11

Keywords

  • MRAM
  • Multi-context
  • Non-Volatile
  • Radiation Hardness by Design
  • SEU
  • Spintronics

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