Skip to main navigation Skip to search Skip to main content

Gate camouflaging-based obfuscation

  • Xueyan Wang
  • , Mingze Gao
  • , Qiang Zhou
  • , Yici Cai
  • , Gang Qu*
  • *Corresponding author for this work
  • Tsinghua University
  • University of Maryland, College Park

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

Abstract

Circuit camouflaging is a layout-level technique to protect VLSI design from being attacked by reverse engineering. It hides design information by configurable logic units that can be configured to perform different functionalities with identical looks to the attackers. In this chapter, after introducing the primitive for gate camouflaging-based obfuscation, we analyze its vulnerability to one specific attack based on circuit partitioning. We then elaborate this attack and discuss two practical countermeasure methods. We explain that the security of gate camouflaging-based obfuscation not only depends on the number of gates being obfuscated, but also which gates we select for obfuscation and the number of different functionalities these gates can implement. As an example, we show how to perform a multiplexer-based gate camouflaging.

Original languageEnglish
Title of host publicationHardware Protection through Obfuscation
PublisherSpringer International Publishing
Pages89-102
Number of pages14
ISBN (Electronic)9783319490199
ISBN (Print)9783319490182
DOIs
StatePublished - 1 Jan 2017
Externally publishedYes

Keywords

  • Circuit camouflaging
  • Circuit partition attack
  • Configurable CMOS
  • Fingerprinting
  • Isolated gates
  • Multiplexer-based obfuscation
  • Reverse engineering
  • Watermarking

Fingerprint

Dive into the research topics of 'Gate camouflaging-based obfuscation'. Together they form a unique fingerprint.

Cite this