Exploring potentials of NAND-like spintronics MRAM for cache design (Invited)

With integration density on-chip rocketing up, leakage power dominates the whole power budget of contemporary CMOS based memory, especially for SRAM based on-chip cache. A few non-volatile technologies especially magnetic random access memory (MRAM) technologies are proposed to deal with this issue. Among them, spin transfer torque (STT) MRAM is a possible candidate for future on-chip cache design. However, as the cache capacity keeps growing, STT-MRAM suffers the bottlenecks on both operation speed and power efficiency. In this context, a new NAND-like spin orbit torque (SOT)-based MRAM, NAND-SPIN, which combines the high density of the STT-MRAM and the high performance of the SOT- MRAM has been proposed. Thanks to these benefits, NAND-SPIN could be more suitable for the future large capacity application. In the paper, we evaluate the NAND-SPIN for on-chip cache design in terms of performance, area and power consumption. The runtime system level experimental results show that NAND- SPIN has higher performance/power efficiency compared to SRAM, STT-MRAM and SOT-MRAM, especially in the large capacity situation.