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Evolution Mechanism of Copper Grains in Advanced Interconnect Processes

  • Yinuo Jin
  • , Han Zhang*
  • , Changqing Zhu
  • , Liang Du
  • , Simian Zhang
  • , Linbo Liu
  • , Qixing Yu
  • , Yu Yao
  • , Rong Yu*
  • , Chen Wang*
  • *Corresponding author for this work
  • Tsinghua University
  • Semiconductor Technology Innovation Center (Beijing) Corporation
  • Inc.
  • Beijing Advanced Innovation Center for Integrated Circuits

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In dual-damascene interconnect applications, the decreasing copper concentration and lower current/voltage in electrochemical plating pose challenges to Cu grain evolution. This paper investigates Cu grain growth in low-Cu plating solutions using two types of seed layers. Results show that larger original grains in CuMn seed layers lead to separation from the electroplated layer. During self-annealing, grains evolve vertically from the bottom upward due to seed stress, and horizontally from the wafer center outward under grain boundary forces. Moreover, precise control of current density can effectively optimize the growth behavior of Cu grains, thereby improving device performance.

Original languageEnglish
Title of host publication2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025
EditorsCor Claeys, Beichao Zhang, Beichao Zhang, Bin Yu, Peng Bai, Qianqian Huang, Xiaowei Li, Steve X. Liang, Hsiang-Lan Lung, Linyong Pang, Weikang Qian, Xinping Qu, Xiaoping Shi, Jianshi Tang, Ying Zhang, Pingqiang Zhou, Cheng Zhuo
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798331513351
DOIs
StatePublished - 2025
Externally publishedYes
Event2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025 - Shanghai, China
Duration: 24 May 202525 May 2025

Publication series

Name2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025

Conference

Conference2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025
Country/TerritoryChina
CityShanghai
Period24/05/2525/05/25

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