Evaluating SEU effects in SRAM-based FPGA with bit-by-bit upset fault injection

Static random access memory (SRAM)-based field programmable gate arrays (FPGAs) are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to evaluate the dependability of the obtained designs, a bit-by-bit upset fault injection methodology based on run-time reconfiguration was proposed. The methodology can detect the sensitive bits in various logic designs. The configuration memories' dynamic cross section, failure rate and reliability change curve can be counted with the number of sensitive bits. The reliability parameters and curves of triple modular redundancy (TMR) multiplier and non-TMR multiplier were obtained with this method, and the correctness of sensitive bits was validated.