ESD Characterisation and Modelling of Digital Integrated Circuits Based on TLP Test

This paper investigates the damage characteristics of digital integrated circuits under transmission line pulse (TLP) stress. Accurate damage data were obtained using TLP test. By analyzing the test results, we found that the same type of loops in the same digital integrated circuit have similar I-V characteristic curves and damage current values, while different types of loops have large differences. This indicates that the design of the electrostatic protection inside the chip has a significant effect on the ESD immunity of the loops. In order to more accurately simulate the loop characteristics of digital integrated circuits, this paper adopts a segmented linear modelling approach. The method is able to effectively consider the nonlinear characteristics of the loop, and the data validation proves that the simulation results are highly consistent with the measured data. The model provides a powerful theoretical support and tool for the design optimization, fault analysis and reliability assessment of digital integrated circuits.