Enabling Energy-Efficient Homomorphic Encryption Evaluation via eDRAM-Based In-Situ Computing in an Edge Processor

This work demonstrates an edge processor featuring programmable and energy-efficient homomorphic encryption (HE) evaluation using in-situ computing (ISC) and in-memory computing (IMC) techniques. HE has been a promising candidate for privacy-preserving computing; however, it is challenged by extreme computation and storage inflation. This has motivated pioneering works on HE hardware in domain-specific accelerator (DSA) forms, whose nature of von Neumann architecture limits their further gains with high-dimensional intermediate ciphertext. The demonstrated processor architecture enables HE evaluation on the edge, addressing intermediate ciphertext’s heavy buffering and swapping overheads. The in-situ HE processing core (ISHEPC) employs tightly coupled dynamic logic and eDRAM bit cells to enable highly dense local storage and parallel programmable computing. An automorphism network implemented at both circuit and architecture levels connects bit cells across ISHEPCs, harnessing chip-level gains with efficient HE data swapping. A silicon prototype integrating eight ISHEPCs with a RISC-V CPU demonstrated in 28-nm CMOS achieves a peak energy efficiency of 3.04 M-NTT/J, a peak throughput of 13.9 k-NTT/s, both with 4096-D 19 bit at 0.8 V, and a local storage density of 2.33 Mb/mm2. This enables 620-k-Op/J CKKS encryption with the same data and voltage configurations. The system demonstration of support-vector-machine (SVM) inference using the CKKS-residue number system (RNS) HE scheme on the LFW dataset achieves 85.5% accuracy with a peak throughput of 2.2 Op/s and a peak energy efficiency of 500 Op/J at 0.8 V.