Abstract
The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads. Finding a feasible worst case workload is difficult due to logical correlation within the logic circuit under consideration. In this article, we propose an NBTI-aware subset simulation (SS) framework that efficiently and accurately finds the failure probability covering various input duty cycles determined by different workloads. In addition, the proposed method is incorporated with the NBTI mitigation technique to facilitate workload-aware mitigation. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to a naive Monte Carlo method. The NBTI mitigation based on SS demonstrates 1.78× better mitigation for multiple input duty cycles compared to the conventional method.
| Original language | English |
|---|---|
| Pages (from-to) | 5515-5525 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 41 |
| Issue number | 12 |
| DOIs | |
| State | Published - 1 Dec 2022 |
Keywords
- Failure probability analysis
- Monte Carlo (MC) simulation
- negative bias temperature instability (NBTI) mitigation
- reliability
- transistor aging
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