Dynamic time tuning for way prediction cache in low power embedded processors

The rapid advances in embedded microprocessor technologies provide opportunities to promote digital avionic systems significantly. With the complexity and frequency increase, power consumption has quickly become a key design constraint in embedded microprocessor designs. The embedded processors in avionic systems must utilize energy efficiently, as their energy payload is restricted by battery factor and weight constraints in aircrafts. This paper proposed a new approaching using dynamic time slice turning with way prediction technology for achieving high performance and low energy consumption in set-associative cache. Among all the cache power saving approaches, prediction cache surpasses others for it reduces power dissipation along with negligible degradation of performance. However, way prediction cache depends heavily on locality principle of programs, especially for programs executed in embedded processor. Time turning way-prediction cache is introduced in this paper to self-adapt time slice turning, according to prediction misses and cache misses in execution interval. Since predictor consumes additional energy itself, dynamic time turning cache allow for proper reconfiguration actions; consequently, it cuts down unnecessary reconfiguration power dissipation. Simulators Sim-Panalyzer and Cacti are chose to estimate the power dissipations of the parameterized architectural components in implementing our dynamic time turning way prediction caches. This method avoids unnecessary reconfiguration actions by adapting program behavior much more intelligently; meanwhile, it keeps performance degradation in a very small scale. Suggested novel cache design in avionic embedded microprocessor satisfies low power and high performance requirement tendency in avionic electronics systems development.