Dual-plane switch architecture for time-triggered ethernet

Meng Dong; Zhiliang Qiu; Weitao Pan; Hongbin Zhang; Chenglei Kong; Hui Jin; Jianlei Yang

doi:10.1145/3386263.3407597

Dual-plane switch architecture for time-triggered ethernet

Meng Dong
, Zhiliang Qiu
, Weitao Pan^*
, Hongbin Zhang
, Chenglei Kong
, Hui Jin
, Jianlei Yang

^*Corresponding author for this work

School of Computer Science and Engineering

Xidian University
Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Time-triggered Ethernet (TTE) technology introduces the concept of time-triggered on the basis of traditional Ethernet, so that it can achieve conflict-free and deterministic service forwarding without sacrificing compatibility. However, storage resources in industrial, aviation, aerospace and other equipment are limited. Therefore, it is important for TTEthernet to develop switching technologies with high storage efficiency and scalability. This paper proposes a dual plane switching (DPS) architecture for TTEthernet, which divides time-triggered services and event-triggered services into two planes for data forwarding. Experimental results show that using the TTE switch of this architecture has the advantages of high clock synchronization accuracy, high throughout, low transmission delay and small jitter of TTE service.

Original language	English
Title of host publication	GLSVLSI 2020 - Proceedings of the 2020 Great Lakes Symposium on VLSI
Publisher	Association for Computing Machinery
Pages	375-379
Number of pages	5
ISBN (Electronic)	9781450379441
DOIs	https://doi.org/10.1145/3386263.3407597
State	Published - 7 Sep 2020
Event	30th Great Lakes Symposium on VLSI, GLSVLSI 2020 - Virtual, Online, China Duration: 7 Sep 2020 → 9 Sep 2020

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	30th Great Lakes Symposium on VLSI, GLSVLSI 2020
Country/Territory	China
City	Virtual, Online
Period	7/09/20 → 9/09/20

Keywords

Dual plane switching architecture
High throughout
Low transmission delay
Time-triggered Ethernet

Access to Document

10.1145/3386263.3407597

Cite this

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title = "Dual-plane switch architecture for time-triggered ethernet",

abstract = "Time-triggered Ethernet (TTE) technology introduces the concept of time-triggered on the basis of traditional Ethernet, so that it can achieve conflict-free and deterministic service forwarding without sacrificing compatibility. However, storage resources in industrial, aviation, aerospace and other equipment are limited. Therefore, it is important for TTEthernet to develop switching technologies with high storage efficiency and scalability. This paper proposes a dual plane switching (DPS) architecture for TTEthernet, which divides time-triggered services and event-triggered services into two planes for data forwarding. Experimental results show that using the TTE switch of this architecture has the advantages of high clock synchronization accuracy, high throughout, low transmission delay and small jitter of TTE service.",

keywords = "Dual plane switching architecture, High throughout, Low transmission delay, Time-triggered Ethernet",

author = "Meng Dong and Zhiliang Qiu and Weitao Pan and Hongbin Zhang and Chenglei Kong and Hui Jin and Jianlei Yang",

note = "Publisher Copyright: {\textcopyright} 2020 Association for Computing Machinery.; 30th Great Lakes Symposium on VLSI, GLSVLSI 2020 ; Conference date: 07-09-2020 Through 09-09-2020",

year = "2020",

month = sep,

day = "7",

doi = "10.1145/3386263.3407597",

language = "英语",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

publisher = "Association for Computing Machinery ",

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address = "美国",

}

Dong, M, Qiu, Z, Pan, W, Zhang, H, Kong, C, Jin, H & Yang, J 2020, Dual-plane switch architecture for time-triggered ethernet. in GLSVLSI 2020 - Proceedings of the 2020 Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Association for Computing Machinery , pp. 375-379, 30th Great Lakes Symposium on VLSI, GLSVLSI 2020, Virtual, Online, China, 7/09/20. https://doi.org/10.1145/3386263.3407597

Dual-plane switch architecture for time-triggered ethernet. / Dong, Meng; Qiu, Zhiliang; Pan, Weitao et al.
GLSVLSI 2020 - Proceedings of the 2020 Great Lakes Symposium on VLSI. Association for Computing Machinery , 2020. p. 375-379 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Pan, Weitao

AU - Zhang, Hongbin

AU - Kong, Chenglei

AU - Jin, Hui

AU - Yang, Jianlei

PY - 2020/9/7

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AB - Time-triggered Ethernet (TTE) technology introduces the concept of time-triggered on the basis of traditional Ethernet, so that it can achieve conflict-free and deterministic service forwarding without sacrificing compatibility. However, storage resources in industrial, aviation, aerospace and other equipment are limited. Therefore, it is important for TTEthernet to develop switching technologies with high storage efficiency and scalability. This paper proposes a dual plane switching (DPS) architecture for TTEthernet, which divides time-triggered services and event-triggered services into two planes for data forwarding. Experimental results show that using the TTE switch of this architecture has the advantages of high clock synchronization accuracy, high throughout, low transmission delay and small jitter of TTE service.

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T2 - 30th Great Lakes Symposium on VLSI, GLSVLSI 2020

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ER -

Dual-plane switch architecture for time-triggered ethernet

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Keywords

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