Design of the writing circuit with a low supply voltage for the spin-transfer torque random access memory

A writing circuit with a low supply voltage for the spin transfer torque magnetic random access memory (STT-MRAM) is proposed to reduce the writing power consumption. Using the combination of the column selecting and the isolation between writing and reading operation, the writing circuit with a low supply voltage decreases the resistor value of the writing branch and the value of the reading current. Therefore the switching power efficiency and the reliability can be improved. By using an accurate compact model of the 65 nm magnetic tunnel junction (MTJ) and a commercial CMOS design-kit, mixed transient and statistical simulations have been performed to validate this design. Simulation results indicate that the proposed circuits can decrease the writing power consumption and improve the reliability.