Design of a K-band fast hopping frequency synthesizer

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Abstract

The design and implementation of a K-band fast hopping frequency synthesizer based on DDS and PLL is described. Main technical specifications are as follows: Frequency ranges from 24GHz to 27GHz, step frequency is 50MHz and lock time is less than 150ns. The parameters of loop filter and the analyses of phase noise and lock time are provided by MATLAB simulation to verify the feasibility of the design. Final test results of the circuits proves that the targets of performance are achieved.

Original languageEnglish
Title of host publication2017 2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages137-140
Number of pages4
ISBN (Electronic)9781538635063
DOIs
StatePublished - 29 Dec 2017
Event2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017 - Nanjing, China
Duration: 8 Nov 201711 Nov 2017

Publication series

Name2017 2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
Volume2017-November

Conference

Conference2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
Country/TerritoryChina
CityNanjing
Period8/11/1711/11/17

Keywords

  • DSS
  • fast hopping
  • K-band
  • lock time
  • PLL

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