Design of a high-throughput QC-LDPC decoder with TDMP scheduling

Low-density parity-check (LDPC) codes with turbo-decoding message-passing (TDMP) scheduling can obtain good performance and high convergence rates. In addition, the min-sum (MS) algorithm can reduce the complexity. The hybrid normalized MS algorithm with TDMP scheduling is presented to achieve good performance and to lower the complexity. For a quasi-cyclic LDPC (QC-LDPC) code with a long code length, parallel degree optimization and an offset iterative sequence rule are proposed. With the proposed techniques, the data correlation problem and memory access conflicts during TDMP scheduling can be resolved so that the iteration can smoothly proceed through the reasonable division of each block row. Fabricated in the 90-nm 1-Poly 9-Metal (1P9M) CMOS process, a multimode 96 000-bit irregular QC-LDPC decoder is implemented. It attains throughputs of 1.7-3.0 Gb/s and dissipates an average power of 502 mW at an operation frequency of 100 MHz and at 10 iterations. The decoder chip area is 13.32 mm², with a core area of 9.73 mm².