Design of a data transmission system based on Gigabit Ethernet

FPGA(Field-programmable gate array) is programmable device, characterized by high speed and reconfiguration. We could test the circuit programmed by HDL (Hardware Description Language). By observing results of simulations through ModelSim, developers could fix logic errors. Also, they could analyze performance of circuits by the results. In the system, we build the Gigabit Ethernet development platform based on a FPGA. This paper presents the technique of FPGA and Gigabit Ethernet, as well as relevant techniques. On the basis of merits and drawbacks of different design proposals and real demands, we take the EP3C10E144C8N chip belonging to the series of Cyclone III produced by Altera corp. as main controller chip. By the use of an AX88180 MAC chip produced by ASIX Electronics Corporation and a RTL8211E physical chip by Realtek Semiconductor Corporation, we build the development platform. At the receiving end, we capture data frames from the network adapter by winpcap programming and throw video data in the buffer. Considering large amounts of data in the real-time transportation, we design fixed-length queue as the primary structures for buffer. Size of a buffer unit is 32KB, which means that 32 packets can fill the buffer. When the buffer is full, we put the buffer unit to the end of the queue. We get data from buffer and hand it over to application process to display and store video data. When packet loss is detected by the system, log file will record it and thus we can check how many packets lose. The simulations by Quartus II and practical application proves that the system is stable, featuring high speed and low cost. It can be used in various high speed real-time transmission with little modification.