Design methods of multi-DSP parallel processing system

Wu Wei; Wang Jun; Li Wei; Zhang Wenhao

doi:10.1109/CSIE.2009.40

Design methods of multi-DSP parallel processing system

Wu Wei^*
, Wang Jun
, Li Wei
, Zhang Wenhao

^*Corresponding author for this work

Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.

Original language	English
Title of host publication	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Pages	458-464
Number of pages	7
DOIs	https://doi.org/10.1109/CSIE.2009.40
State	Published - 2009
Event	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009 - Los Angeles, CA, United States Duration: 31 Mar 2009 → 2 Apr 2009

Publication series

Name	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Volume	3

Conference

Conference	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Country/Territory	United States
City	Los Angeles, CA
Period	31/03/09 → 2/04/09

Access to Document

10.1109/CSIE.2009.40

Cite this

@inproceedings{30acc1bce2ec45498dc3f40157949cf9,

title = "Design methods of multi-DSP parallel processing system",

abstract = "In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.",

author = "Wu Wei and Wang Jun and Li Wei and Zhang Wenhao",

year = "2009",

doi = "10.1109/CSIE.2009.40",

language = "英语",

isbn = "9780769535074",

series = "2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009",

pages = "458--464",

booktitle = "2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009",

note = "2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009 ; Conference date: 31-03-2009 Through 02-04-2009",

}

Wei, W, Jun, W , Wei, L & Wenhao, Z 2009, Design methods of multi-DSP parallel processing system. in 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009., 5170884, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, vol. 3, pp. 458-464, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, Los Angeles, CA, United States, 31/03/09. https://doi.org/10.1109/CSIE.2009.40

Design methods of multi-DSP parallel processing system. / Wei, Wu; Jun, Wang ; Wei, Li et al.
2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009. 2009. p. 458-464 5170884 (2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wei, Wu

AU - Jun, Wang

AU - Wei, Li

AU - Wenhao, Zhang

PY - 2009

Y1 - 2009

N2 - In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.

AB - In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.

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DO - 10.1109/CSIE.2009.40

M3 - 会议稿件

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SN - 9780769535074

T3 - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009

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BT - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009

T2 - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009

Y2 - 31 March 2009 through 2 April 2009

ER -

Design methods of multi-DSP parallel processing system

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