Design and optimization of an area-efficient SOT-MRAM

Chao Wang; Zhaohao Wang; Bi Wu; Weisheng Zhao

doi:10.1109/EDSSC.2019.8754166

Design and optimization of an area-efficient SOT-MRAM

Chao Wang
, Zhaohao Wang
, Bi Wu
, Weisheng Zhao

School of Integrated Circuit Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

Spin orbit torque magnetic random access memory (SOT-MRAM) has attracted numerous research interests since it promises to overcome the write speed and energy bottlenecks of the conventional STT-MRAM. However, the cell density of SOT-MRAM is constrained due to more access transistors. In this work, we present a NAND-Like architecture for SOT-MRAM with a single transistor and several diodes, as well as a novel adaptive array design based on the proposed cell structure. Compared with the standard SOTMRAM, the proposed SOT-MRAM achieves significant improvement in the cell density by sharing transistors, meanwhile attains a comparable write speed. The overhead of write energy can be compensated by a well-designed write policy.

Original language	English
Title of host publication	2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728102863
DOIs	https://doi.org/10.1109/EDSSC.2019.8754166
State	Published - Jun 2019
Event	2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019 - Xi'an, China Duration: 12 Jun 2019 → 14 Jun 2019

Publication series

Name	2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019

Conference

Conference	2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019
Country/Territory	China
City	Xi'an
Period	12/06/19 → 14/06/19

Keywords

High density
Magnetic random access memory (MRAM)
Spin orbit torque (SOT)
Write policy

Access to Document

10.1109/EDSSC.2019.8754166

Cite this

Wang, C., Wang, Z., Wu, B., & Zhao, W. (2019). Design and optimization of an area-efficient SOT-MRAM. In 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019 Article 8754166 (2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2019.8754166

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title = "Design and optimization of an area-efficient SOT-MRAM",

abstract = "Spin orbit torque magnetic random access memory (SOT-MRAM) has attracted numerous research interests since it promises to overcome the write speed and energy bottlenecks of the conventional STT-MRAM. However, the cell density of SOT-MRAM is constrained due to more access transistors. In this work, we present a NAND-Like architecture for SOT-MRAM with a single transistor and several diodes, as well as a novel adaptive array design based on the proposed cell structure. Compared with the standard SOTMRAM, the proposed SOT-MRAM achieves significant improvement in the cell density by sharing transistors, meanwhile attains a comparable write speed. The overhead of write energy can be compensated by a well-designed write policy.",

keywords = "High density, Magnetic random access memory (MRAM), Spin orbit torque (SOT), Write policy",

author = "Chao Wang and Zhaohao Wang and Bi Wu and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019 ; Conference date: 12-06-2019 Through 14-06-2019",

year = "2019",

month = jun,

doi = "10.1109/EDSSC.2019.8754166",

language = "英语",

series = "2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019",

address = "美国",

}

Wang, C, Wang, Z, Wu, B & Zhao, W 2019, Design and optimization of an area-efficient SOT-MRAM. in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019., 8754166, 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019, Xi'an, China, 12/06/19. https://doi.org/10.1109/EDSSC.2019.8754166

Design and optimization of an area-efficient SOT-MRAM. / Wang, Chao; Wang, Zhaohao; Wu, Bi et al.
2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8754166 (2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Design and optimization of an area-efficient SOT-MRAM

AU - Wang, Chao

AU - Wang, Zhaohao

AU - Wu, Bi

AU - Zhao, Weisheng

PY - 2019/6

Y1 - 2019/6

N2 - Spin orbit torque magnetic random access memory (SOT-MRAM) has attracted numerous research interests since it promises to overcome the write speed and energy bottlenecks of the conventional STT-MRAM. However, the cell density of SOT-MRAM is constrained due to more access transistors. In this work, we present a NAND-Like architecture for SOT-MRAM with a single transistor and several diodes, as well as a novel adaptive array design based on the proposed cell structure. Compared with the standard SOTMRAM, the proposed SOT-MRAM achieves significant improvement in the cell density by sharing transistors, meanwhile attains a comparable write speed. The overhead of write energy can be compensated by a well-designed write policy.

AB - Spin orbit torque magnetic random access memory (SOT-MRAM) has attracted numerous research interests since it promises to overcome the write speed and energy bottlenecks of the conventional STT-MRAM. However, the cell density of SOT-MRAM is constrained due to more access transistors. In this work, we present a NAND-Like architecture for SOT-MRAM with a single transistor and several diodes, as well as a novel adaptive array design based on the proposed cell structure. Compared with the standard SOTMRAM, the proposed SOT-MRAM achieves significant improvement in the cell density by sharing transistors, meanwhile attains a comparable write speed. The overhead of write energy can be compensated by a well-designed write policy.

KW - High density

KW - Magnetic random access memory (MRAM)

KW - Spin orbit torque (SOT)

KW - Write policy

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M3 - 会议稿件

AN - SCOPUS:85069456869

T3 - 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019

BT - 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019

Y2 - 12 June 2019 through 14 June 2019

ER -

Wang C, Wang Z, Wu B, Zhao W. Design and optimization of an area-efficient SOT-MRAM. In 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8754166. (2019 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2019). doi: 10.1109/EDSSC.2019.8754166

Design and optimization of an area-efficient SOT-MRAM

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