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Design and Implementation of IP Core for 1553B bus test

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

MIL-STD-1553B is an avionics bus which is adopted widely, but the 1553B ASIC is difficult to be reprogrammed and modified. Most 1553B applications currently interface via dedicated protocol chip, such as BU-61580, resulting in inferior flexibility and high spending. In this paper, the architecture, function and realization of IP core for implementing 1553B protocol on field programmable device is discussed. The other important point is to raise the fault injection and error detection design method at the protocol layer of IP core. Finally, the experiment results show that the IP core can accord with communication protocol and realize bus test functionality.

Original languageEnglish
Title of host publicationProceedings of the 2015 10th IEEE Conference on Industrial Electronics and Applications, ICIEA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1608-1612
Number of pages5
ISBN (Electronic)9781467373173
DOIs
StatePublished - 20 Nov 2015
Event10th IEEE Conference on Industrial Electronics and Applications, ICIEA 2015 - Auckland, New Zealand
Duration: 15 Jun 201517 Jun 2015

Publication series

NameProceedings of the 2015 10th IEEE Conference on Industrial Electronics and Applications, ICIEA 2015

Conference

Conference10th IEEE Conference on Industrial Electronics and Applications, ICIEA 2015
Country/TerritoryNew Zealand
CityAuckland
Period15/06/1517/06/15

Keywords

  • 1553B bus
  • bus test
  • fault injection
  • IP core
  • VerilogHDL

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