Design and implementation of an adaptive interference mitigation algorithm based on FPGA

As the most advanced Controlled Reception Pattern Antenna (CRPA) technology, Space-Time Adaptive Processing (STAP) is finding its place in interference mitigation in satellite navigation receivers. But the computational burden of STAP increases significantly along with the performance improvement, which makes reduced-rank algorithms critical for real-time processing. This paper focuses on an effective reduced-rank algorithm of Multistage Nested Wiener Filter (MSNWF) applicable to hardware implementation -Iterative Correlation Subtraction Algorithm (ICSA) and its Field Programmable Gate Array (FPGA) design in float point format. The antenna gain pattern, convergence speed, rank reduction capability and interference mitigation performance are simulated in various interference scenarios. The hardware implementation takes full advantage of FPGA parallel computing. The simulation result based on the joint simulation platform of Matlab and Modelsim shows high processing precision, low signal distortion, and real-time property of the design.