Design and FPGA-Based Realization of a Chaotic Secure Video Communication System

This paper initiates a systematic methodology for real-time chaos-based video encryption and decryption communications on the system design and algorithm analysis. The proposed system design and algorithm analysis have been validated on an FPGA hardware platform via Verilog Hardware Description Language (Verilog HDL). Based on the fundamental anti-control principles of dynamical systems, a 6-D real domain chaotic system is designed, and then the corresponding Verilog HDL algorithm is developed. The proposed Verilog HDL algorithm is utilized to design a real-time chaos-based secure video communication system, with a generalized design principle derived, which is implemented on an FPGA hardware platform equipped with an XUP Virtex-II chip. Following this line, the designed working mechanism is demonstrated by hardware experiments. The security performance is tested using the TESTU01 statistical test suites, the differential analysis, and the sensitivity of key parameters mismatch. Both theoretical analysis and experimental results validate the feasibility and reliability of the proposed system.