Design and ARM-embedded implementation of a chaotic secure communication scheme based on H.264 selective encryption

In this paper, a novel video chaotic secure communication scheme and its ARM-embedded hardware implementation are investigated, based on the H.264 selective encryption and multi-core multi-process. A six-dimensional discrete-time hyperchaotic system equipped with a nonlinear nominal matrix is firstly constructed, and the corresponding chaotic encryption algorithm is then designed. During H.264 encoding, the difference components of motion vectors in both the horizontal and vertical directions, as well as the DC transform coefficients, are selectively encrypted by using such a chaotic encryption algorithm, respectively, so as to enhance the safety performance. To improve the processing speed and transmission frame rate of the whole hardware system, an ARM-based hardware platform with multi-core multi-process is further adopted to realize the H.264 selective video chaotic secure communication, where the sender collects and encrypts the original video with four-core four-process mode, and the receiver decrypts the encrypted video with three-core three-process mode, in which one core binds one process. Finally, the security performance of the designed system is tested using the TESTU01 statistical test suites and some other statistical security analysis. Both theoretical analysis and experimental results validate the feasibility and reliability of the proposed scheme.