Demonstration of 128 Kb SOT-MRAM chip with 5 ns write and 15 ns read speed, high endurance over 10¹⁰and low ECC-on bit error rate

Three-terminal spin-orbit torque (SOT) MRAM attracts great interests in industry but faces integration challenges. In this paper, we succeed in demonstration of the 128 Kb SOT-MRAM chip. Thanks to the process improvement to remove the redeposition, the in-die function yield of the 128 Kb chip is greater than 99.9%. Besides, through reducing the size and optimizing the films, we are able to reduce the critical switching current (Ic) by 25%. The fabricated 128 Kb chip can achieve 5 ns write speed in an industrial-level temperature ranging from -40 °C to 125 °C. The read speed can reach 15 ns. In addition to superior write/read performance, the endurance over 1010 cycles and high data retention over 10 years at the operating temperature are demonstrated. Moreover, we propose a multi-pulse write method to solve the intermediate state issue of the magnetic tunnel junction (MTJ). Finally, recurring to the Hamming error checking and correcting (ECC) based on FPGA, we succeed in a 0-bit-error-rate 128 Kb chip. Our effort will help to expedite the SOT-MRAM to go to the market.