@inproceedings{b2bc6041f4ec4b60878ab3fc3c4f2431,
title = "Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors",
abstract = "In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrodinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.",
keywords = "CMOS, TCAD, electrostatics, nanowire transistors, performance, quantum effects",
author = "Talib Al-Ameri and Y. Wang and Georgiev, \{V. P.\} and F. Adamu-Lema and X. Wang and A. Asenov",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 ; Conference date: 12-09-2015 Through 16-09-2015",
year = "2016",
month = mar,
day = "22",
doi = "10.1109/NMDC.2015.7439240",
language = "英语",
series = "2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015",
address = "美国",
}