@inproceedings{dbef84b542f6409b847df9a1ed10e5d1,
title = "Configuration circuit design for burn-in test of CLB based on structure",
abstract = "As the wide usage of FPGA (Field Programming Gate Array) in military and aerospace fields, the reliability of FPGA becomes more and more significant. CLB (Configurable Logic Block) is the main logic unit of FPGA, which can realize combinational logic and sequential logic. Dynamic burn-in test is one of the most important tests in reliability assessment of FPGA, which can make potential defects of FPGA exposed. In this paper, the structure and layout of Xilinx Spartan-3 FPGA are analyzed. Combined with the problems of FPGA burn-in, configuration circuit based on structure of CLB is designed. SliceMs are configured into RAM chain mode and shift register mode. SliceLs are configured into 4-input XOR chain mode and 4-input NXOR mode. According to the simulation results, the proposed configuration circuit is input-controllable and output-observable, and the resource utilization is improved.",
keywords = "Burn-in, CLB, Configuration Circuit, FPGA, Reliability",
author = "Cheng Gao and Haitian Liu and Xiangfen Wang and Jiaoying Huang",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; Prognostics and System Health Management Conference, PHM 2015 ; Conference date: 21-10-2015 Through 23-10-2015",
year = "2016",
month = jan,
day = "12",
doi = "10.1109/PHM.2015.7380071",
language = "英语",
series = "Proceedings of 2015 Prognostics and System Health Management Conference, PHM 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Tingdi Zhao and Pecht, \{Michael G.\} and Shunong Zhang",
booktitle = "Proceedings of 2015 Prognostics and System Health Management Conference, PHM 2015",
address = "美国",
}