TY - GEN
T1 - Compact modelling for Co/BTO/LSMO Ferroelectric Tunnel Junction
AU - Wang, Zhaohao
AU - Zhao, Weisheng
AU - Bouchenak-Khelladi, Anes
AU - Zhang, Yue
AU - Lin, Weiwei
AU - Klein, Jacques Olivier
AU - Ravelosona, Dafiné
AU - Chappert, Claude
PY - 2013
Y1 - 2013
N2 - Ferroelectric Tunnel Junction (FTJ) is able to store non-volatile data in the spontaneous polarization direction of ferroelectric tunnel barrier. Recent progress have demonstrated its great potential to build up the next generation Non-volatile Memory and Logic (NVM and NVL) thanks to the high OFF/ON resistance ratio, fast operation speed, low write power, non-destructive readout and so on. In this paper, we present the first compact model for Co/BTO/LSMO FTJ nanopillar, which was reported experimentally to exhibit excellent NVM performance. This model integrates related physical models of tunnel resistance, static coercive voltage and dynamic switching delay. Its accuracy is shown by the good agreement between numerical model simulation and experimental measurements. This compact model has been developed in Verilog-A language and implemented on Cadence Virtuoso Platform. Simulations validated the static and dynamic behaviors of this model, indicating that it can be efficiently used for the analysis and design of hybrid FTJ/CMOS circuits.
AB - Ferroelectric Tunnel Junction (FTJ) is able to store non-volatile data in the spontaneous polarization direction of ferroelectric tunnel barrier. Recent progress have demonstrated its great potential to build up the next generation Non-volatile Memory and Logic (NVM and NVL) thanks to the high OFF/ON resistance ratio, fast operation speed, low write power, non-destructive readout and so on. In this paper, we present the first compact model for Co/BTO/LSMO FTJ nanopillar, which was reported experimentally to exhibit excellent NVM performance. This model integrates related physical models of tunnel resistance, static coercive voltage and dynamic switching delay. Its accuracy is shown by the good agreement between numerical model simulation and experimental measurements. This compact model has been developed in Verilog-A language and implemented on Cadence Virtuoso Platform. Simulations validated the static and dynamic behaviors of this model, indicating that it can be efficiently used for the analysis and design of hybrid FTJ/CMOS circuits.
KW - Compact model
KW - Ferroelectric Tunnel Junction
KW - Non-volatile
KW - Static and dynamic behavior
UR - https://www.scopus.com/pages/publications/84894199793
U2 - 10.1109/NANO.2013.6720853
DO - 10.1109/NANO.2013.6720853
M3 - 会议稿件
AN - SCOPUS:84894199793
SN - 9781479906758
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 229
EP - 232
BT - 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013
T2 - 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013
Y2 - 5 August 2013 through 8 August 2013
ER -