BIST-based method for diagnosing multiple faulty CLBs in FPGAs

  • Guo Hua Wang*
  • , Jing Lin Sun
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a new built-in self test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distributed RAM mode of the memory block, the TPG based on FSM is designed to provide March C- testing patterns. Besides, the comparator-based output response analyzer (ORA) and the cascaded ORA scan chain are used to locate the faulty CLB and propagate the comparison output in every row. Finally, fault-injection experiment results verify its ability to detect and diagnose multiple faulty CLBs in faulty FPGAs.

Original languageEnglish
Title of host publicationEngineering Providing of Industrial Development
EditorsWen Jin
PublisherTrans Tech Publications Ltd
Pages243-248
Number of pages6
ISBN (Electronic)9783038352433
DOIs
StatePublished - 2014
Event2nd Asian Pacific Conference on Mechatronics and Control Engineering, APCMCE 2014 - Hong Kong, China
Duration: 8 Aug 20149 Aug 2014

Publication series

NameApplied Mechanics and Materials
Volume643
ISSN (Print)1660-9336
ISSN (Electronic)1662-7482

Conference

Conference2nd Asian Pacific Conference on Mechatronics and Control Engineering, APCMCE 2014
Country/TerritoryChina
CityHong Kong
Period8/08/149/08/14

Keywords

  • BIST
  • Fault diagnosis
  • March C-
  • Pseudo-exhaustive testing
  • Scan chain

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