Architecture design with STT-RAM: Opportunities and challenges

Ping Chi; Shuangchen Li; Yuanqing Cheng; Yu Lu; Seung H. Kang; Yuan Xie

doi:10.1109/ASPDAC.2016.7427997

Architecture design with STT-RAM: Opportunities and challenges

Ping Chi
, Shuangchen Li
, Yuanqing Cheng
, Yu Lu
, Seung H. Kang
, Yuan Xie

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

44 Scopus citations

Abstract

The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than SRAM, also bring design challenges. This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the cache and memory system design by taking advantage of the opportunities brought by STT-RAM as well as overcoming the challenges.

Original language	English
Title of host publication	2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	109-114
Number of pages	6
ISBN (Electronic)	9781467395694
DOIs	https://doi.org/10.1109/ASPDAC.2016.7427997
State	Published - 7 Mar 2016
Externally published	Yes
Event	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao SAR Duration: 25 Jan 2016 → 28 Jan 2016

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	25-28-January-2016

Conference

Conference	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Country/Territory	Macao SAR
City	Macao
Period	25/01/16 → 28/01/16

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/ASPDAC.2016.7427997

Cite this

Chi, P., Li, S., Cheng, Y., Lu, Y., Kang, S. H., & Xie, Y. (2016). Architecture design with STT-RAM: Opportunities and challenges. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 109-114). Article 7427997 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7427997

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title = "Architecture design with STT-RAM: Opportunities and challenges",

abstract = "The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than SRAM, also bring design challenges. This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the cache and memory system design by taking advantage of the opportunities brought by STT-RAM as well as overcoming the challenges.",

author = "Ping Chi and Shuangchen Li and Yuanqing Cheng and Yu Lu and Kang, \{Seung H.\} and Yuan Xie",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 ; Conference date: 25-01-2016 Through 28-01-2016",

year = "2016",

month = mar,

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doi = "10.1109/ASPDAC.2016.7427997",

language = "英语",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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Chi, P, Li, S, Cheng, Y, Lu, Y, Kang, SH & Xie, Y 2016, Architecture design with STT-RAM: Opportunities and challenges. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016., 7427997, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 25-28-January-2016, Institute of Electrical and Electronics Engineers Inc., pp. 109-114, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao SAR, 25/01/16. https://doi.org/10.1109/ASPDAC.2016.7427997

Architecture design with STT-RAM: Opportunities and challenges. / Chi, Ping; Li, Shuangchen; Cheng, Yuanqing et al.
2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 109-114 7427997 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Architecture design with STT-RAM

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AU - Chi, Ping

AU - Li, Shuangchen

AU - Cheng, Yuanqing

AU - Lu, Yu

AU - Kang, Seung H.

AU - Xie, Yuan

PY - 2016/3/7

Y1 - 2016/3/7

N2 - The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than SRAM, also bring design challenges. This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the cache and memory system design by taking advantage of the opportunities brought by STT-RAM as well as overcoming the challenges.

AB - The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than SRAM, also bring design challenges. This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the cache and memory system design by taking advantage of the opportunities brought by STT-RAM as well as overcoming the challenges.

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Chi P, Li S, Cheng Y, Lu Y, Kang SH, Xie Y. Architecture design with STT-RAM: Opportunities and challenges. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 109-114. 7427997. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2016.7427997

Architecture design with STT-RAM: Opportunities and challenges

Abstract

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