Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance

Yulong Qiu; Chao Wang; Zhongzhen Tong; Siyuan Cheng; Yueting Li; Zhaohao Wang

doi:10.1109/ISCAS56072.2025.11043691

Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance

Yulong Qiu
, Chao Wang^*
, Zhongzhen Tong
, Siyuan Cheng
, Yueting Li
, Zhaohao Wang

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Magnetoresistive random-access memory (MRAM) has been demonstrated to be a suitable memory technology for neural network (NN) acceleration due to its non-volatility, high density, and fast access speed. However, compared to the widely used static random-access memory (SRAM), MRAM still exhibits a notable disparity in speed and energy. In this paper, we propose a read-related approximation computation (RAC) strategy based on spin-orbit torque MRAM (SOT-MRAM) to enhance the computational speed of NN, and then we introduce a reference reconfigurable array (RRA) architecture to further decrease the read latency and energy consumption, significantly improving the speed and energy efficiency of weight retrieval during computations. Furthermore, we propose an algorithm to verify and optimize NN model performance. The proposed architecture is evaluated using a 28 nm process combined with a SPICE model of the SOT-MRAM. Simulation results indicate that the read speed increases by 4.71X, the read energy consumption is reduced by 70.7%, while the model accuracy loss remains below 1%.

Original language	English
Title of host publication	ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350356830
DOIs	https://doi.org/10.1109/ISCAS56072.2025.11043691
State	Published - 2025
Event	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom Duration: 25 May 2025 → 28 May 2025

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/Territory	United Kingdom
City	London
Period	25/05/25 → 28/05/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

AI Acceleration
Approximate computing
Near-Memory Computing (NMC)
Quantized Neural Networks (QNN)
SOT-MRAM

Access to Document

10.1109/ISCAS56072.2025.11043691

Cite this

Qiu, Y., Wang, C., Tong, Z., Cheng, S., Li, Y., & Wang, Z. (2025). Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance. In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS56072.2025.11043691

@inproceedings{e74e515c4abc482483206fa9c41cb9ab,

title = "Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance",

abstract = "Magnetoresistive random-access memory (MRAM) has been demonstrated to be a suitable memory technology for neural network (NN) acceleration due to its non-volatility, high density, and fast access speed. However, compared to the widely used static random-access memory (SRAM), MRAM still exhibits a notable disparity in speed and energy. In this paper, we propose a read-related approximation computation (RAC) strategy based on spin-orbit torque MRAM (SOT-MRAM) to enhance the computational speed of NN, and then we introduce a reference reconfigurable array (RRA) architecture to further decrease the read latency and energy consumption, significantly improving the speed and energy efficiency of weight retrieval during computations. Furthermore, we propose an algorithm to verify and optimize NN model performance. The proposed architecture is evaluated using a 28 nm process combined with a SPICE model of the SOT-MRAM. Simulation results indicate that the read speed increases by 4.71X, the read energy consumption is reduced by 70.7\%, while the model accuracy loss remains below 1\%.",

keywords = "AI Acceleration, Approximate computing, Near-Memory Computing (NMC), Quantized Neural Networks (QNN), SOT-MRAM",

author = "Yulong Qiu and Chao Wang and Zhongzhen Tong and Siyuan Cheng and Yueting Li and Zhaohao Wang",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",

year = "2025",

doi = "10.1109/ISCAS56072.2025.11043691",

language = "英语",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",

address = "美国",

}

Qiu, Y, Wang, C, Tong, Z, Cheng, S, Li, Y & Wang, Z 2025, Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance. in ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11043691

Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance. / Qiu, Yulong; Wang, Chao; Tong, Zhongzhen et al.
ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance

AU - Qiu, Yulong

AU - Wang, Chao

AU - Tong, Zhongzhen

AU - Cheng, Siyuan

AU - Li, Yueting

AU - Wang, Zhaohao

PY - 2025

Y1 - 2025

N2 - Magnetoresistive random-access memory (MRAM) has been demonstrated to be a suitable memory technology for neural network (NN) acceleration due to its non-volatility, high density, and fast access speed. However, compared to the widely used static random-access memory (SRAM), MRAM still exhibits a notable disparity in speed and energy. In this paper, we propose a read-related approximation computation (RAC) strategy based on spin-orbit torque MRAM (SOT-MRAM) to enhance the computational speed of NN, and then we introduce a reference reconfigurable array (RRA) architecture to further decrease the read latency and energy consumption, significantly improving the speed and energy efficiency of weight retrieval during computations. Furthermore, we propose an algorithm to verify and optimize NN model performance. The proposed architecture is evaluated using a 28 nm process combined with a SPICE model of the SOT-MRAM. Simulation results indicate that the read speed increases by 4.71X, the read energy consumption is reduced by 70.7%, while the model accuracy loss remains below 1%.

AB - Magnetoresistive random-access memory (MRAM) has been demonstrated to be a suitable memory technology for neural network (NN) acceleration due to its non-volatility, high density, and fast access speed. However, compared to the widely used static random-access memory (SRAM), MRAM still exhibits a notable disparity in speed and energy. In this paper, we propose a read-related approximation computation (RAC) strategy based on spin-orbit torque MRAM (SOT-MRAM) to enhance the computational speed of NN, and then we introduce a reference reconfigurable array (RRA) architecture to further decrease the read latency and energy consumption, significantly improving the speed and energy efficiency of weight retrieval during computations. Furthermore, we propose an algorithm to verify and optimize NN model performance. The proposed architecture is evaluated using a 28 nm process combined with a SPICE model of the SOT-MRAM. Simulation results indicate that the read speed increases by 4.71X, the read energy consumption is reduced by 70.7%, while the model accuracy loss remains below 1%.

KW - AI Acceleration

KW - Approximate computing

KW - Near-Memory Computing (NMC)

KW - Quantized Neural Networks (QNN)

KW - SOT-MRAM

UR - https://www.scopus.com/pages/publications/105010651983

U2 - 10.1109/ISCAS56072.2025.11043691

DO - 10.1109/ISCAS56072.2025.11043691

M3 - 会议稿件

AN - SCOPUS:105010651983

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025

Y2 - 25 May 2025 through 28 May 2025

ER -

Qiu Y, Wang C, Tong Z, Cheng S, Li Y, Wang Z. Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance. In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2025. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS56072.2025.11043691

Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance

Abstract

Publication series

Conference

UN SDGs

Keywords

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