Anti-Harmonic Phase Detector for PLL in Resolver-to-Digital Conversion

In resolver-to-digital conversion (RDC), phase-locked loop (PLL) employs a phase detector (PD) to discriminate the error between the actual and estimated phase angles. However, there are inevitable harmonics in resolver signals which will cause undesired harmonics in the phase detection error and thus degrade RDC accuracy. In this article, an anti-harmonic phase detector (AHPD) is proposed to reject harmonics in the phase detection error. First, the amplitude of each harmonic is estimated by designing a gradient estimator in the d-axis component from Park transformation of resolver envelopes. Since the d-axis component is not involved in PLL, the dynamics of the estimator is immune to that of PLL. Second, the harmonics in the q-axis component are constructed and then compensated by using the estimated harmonic amplitudes in the d-axis component based on the orthogonality and symmetry in the pair axes. Thus, the undesired harmonics in the detection error can be converted into approximately linear functions of the actual phase error which will converge to zero with the detection error driven by PLL. Simulation and experimental results demonstrate the effectiveness of the proposed method.