An Improved Synchronization Method for FPGA Based Broadband Satellite Receiver

This paper presents an improved synchronization method based broadband satellite receiver, focusing on timing synchronization and carrier synchronization, with hardware implementation carried out on an FPGA. The designed receiver system can accept 32 parallel input channels, achieving data input rates up to Gsps levels. For the timing synchronization, an improved structure for the interpolating filter is developed based on the Gardner algorithm, and the timing error estimation formula is refined, ultimately reducing the estimated timing error and enabling the system to achieve timing synchronization more rapidly. For the carrier synchronization, an improved phase detector structure is proposed based on the PFD algorithm, utilizing an Arctan approximation algorithm in place of the Cordic IP core, significantly reducing algorithm delay and hardware resource utilization. Furthermore, the hardware implementation on the FPGA demonstrates the innovation and superiority of the work presented in this paper by comparing the outputs before and after the improvements.