@inproceedings{a2e170d70963412d8bc2ef0777801fe6,
title = "An FPGA-Based High-Speed Reconfigurable Accelerator for YOLO",
abstract = "This work proposes an instruction-driven reconfigurable high-speed accelerator architecture. By dynamically loading precompiled instruction sequences, it enables the flexible deployment of detection algorithms and effectively avoids frequent circuit synthesis processes. Integrating streaming dataflow, sliding-window mechanisms, and digital signal processor (DSP) reuse techniques, the proposed design is verified on the Xilinx XC7Z100-2FFG900 FPGA platform with YOLOv5n as the benchmark network. It achieves a low per-frame latency of 25 ms, representing a 2.8{\texttimes} reduction in inference latency compared to the central processing unit (CPU). Meanwhile, the utilization rates of look-up tables (LUTs) and block random-access memory (BRAM) are reduced by 37.5\% and 24.5\% respectively, significantly enhancing the high-speed processing performance and versatility in resource-constrained hardware environments.",
author = "Hanran Gao and Yulong Qiu and Zhongzhen Tong and Chao Wang and Jianlei Yang and Zhaohao Wang",
note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026 ; Conference date: 22-03-2026 Through 24-03-2026",
year = "2026",
doi = "10.1109/CSTIC68613.2026.11537573",
language = "英语",
series = "2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Cor Claeys and Bin Yu and Beichao Zhang and Peng Bai and Qianqian Huang and Xiaowei Li and Liang, \{Steve X.\} and Hsiang-Lan Lung and Linyong Pang and Xinping Qu and Xiaoping Shi and Jianshi Tang and Pingqiang Zhou and Cheng Zhuo",
booktitle = "2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026",
address = "美国",
}