An execution decoupled fault-tolerant processor

A fault-tolerant processor microarchitecture mainly utilizing temporal redundancy technique is introduced in this paper. The fault-tolerance mechanism is implemented by modifying superscalar processor architecture, which can detect and recover all transient faults and restricted permanent faults. Compared with similar scheme, the major improvement of our fault-tolerant approach is decoupled execution of redundent instruction stream. Simulation results show that the fault-tolerant processor achieves high fault coverage while processor performance degradation is reduced.