An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM

Deyang Yu; Chenchen Liu; Chuanjie Zhang; Xiao Fang; Weisheng Zhao

doi:10.1109/ISCAS66217.2026.11562201

An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM

Deyang Yu
, Chenchen Liu^*
, Chuanjie Zhang
, Xiao Fang
, Weisheng Zhao

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit-Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is encoded as spikes using lightweight circuits, eliminating the need for conventional area- and power-intensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs.

Original language	English
Title of host publication	ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1167-1171
Number of pages	5
ISBN (Electronic)	9798331577698
DOIs	https://doi.org/10.1109/ISCAS66217.2026.11562201
State	Published - 2026
Event	2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026 - Shanghai, China Duration: 24 May 2026 → 27 May 2026

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026
Country/Territory	China
City	Shanghai
Period	24/05/26 → 27/05/26

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

computing-in-memory
spiking processing
Spin-Orbit Torque MRAM

Access to Document

10.1109/ISCAS66217.2026.11562201

Cite this

Yu, D., Liu, C., Zhang, C., Fang, X., & Zhao, W. (2026). An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM. In ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems (pp. 1167-1171). (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS66217.2026.11562201

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title = "An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM",

abstract = "The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit-Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is encoded as spikes using lightweight circuits, eliminating the need for conventional area- and power-intensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs.",

keywords = "computing-in-memory, spiking processing, Spin-Orbit Torque MRAM",

author = "Deyang Yu and Chenchen Liu and Chuanjie Zhang and Xiao Fang and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026 ; Conference date: 24-05-2026 Through 27-05-2026",

year = "2026",

doi = "10.1109/ISCAS66217.2026.11562201",

language = "英语",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems",

address = "美国",

}

Yu, D, Liu, C, Zhang, C, Fang, X & Zhao, W 2026, An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM. in ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1167-1171, 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai, China, 24/05/26. https://doi.org/10.1109/ISCAS66217.2026.11562201

An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM. / Yu, Deyang; Liu, Chenchen; Zhang, Chuanjie et al.
ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2026. p. 1167-1171 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM

AU - Yu, Deyang

AU - Liu, Chenchen

AU - Zhang, Chuanjie

AU - Fang, Xiao

AU - Zhao, Weisheng

PY - 2026

Y1 - 2026

N2 - The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit-Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is encoded as spikes using lightweight circuits, eliminating the need for conventional area- and power-intensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs.

AB - The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit-Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is encoded as spikes using lightweight circuits, eliminating the need for conventional area- and power-intensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs.

KW - computing-in-memory

KW - spiking processing

KW - Spin-Orbit Torque MRAM

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M3 - 会议稿件

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ER -

An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM

Abstract

Publication series

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UN SDGs

Keywords

Access to Document

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