TY - GEN
T1 - An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications
AU - Li, Liangchen
AU - Wu, Jianxin
AU - Li, Changyu
AU - Zhang, Liang
AU - Yu, Anyang
AU - Zhao, Junda
AU - Wang, Zhaohao
AU - Sun, Chengyuan
AU - Cao, Kaihua
AU - Liu, Hongxi
AU - Kang, Wang
AU - Zhang, He
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Downlink precoding in massive multiple input multiple output (MIMO) systems involves high-dimensional sparse matrix calculations, which poses challenges to existing architectures. Computing-in-memory (CIM) has significant advantages in handling large-scale parallel operations, but sparse computing for wireless communication remains underexplored. In this paper, we propose a novel CIM accelerator based on magnetic random access memory (MRAM) leveraging adaptive multi-sparse mode technology for optimized sparse matrix multiplication in MIMO communication systems. This architecture represents the first application of CIM technology for processing sparse matrices in MIMO precoding tasks, minimizing storage requirements and enhancing parallel processing speed. Experimental results demonstrate that, for a 32×256×8 MIMO downlink precoding task with 90% sparsity, the symbol error rate is reduced to 0.1% at a signal-to-noise ratio of 20dB, achieving 8.35× reduction in storage overhead, 39.4× power saving and 9.85× speedup. These results position our accelerator as a promising candidate for processing sparse data in 5G massive MIMO systems.
AB - Downlink precoding in massive multiple input multiple output (MIMO) systems involves high-dimensional sparse matrix calculations, which poses challenges to existing architectures. Computing-in-memory (CIM) has significant advantages in handling large-scale parallel operations, but sparse computing for wireless communication remains underexplored. In this paper, we propose a novel CIM accelerator based on magnetic random access memory (MRAM) leveraging adaptive multi-sparse mode technology for optimized sparse matrix multiplication in MIMO communication systems. This architecture represents the first application of CIM technology for processing sparse matrices in MIMO precoding tasks, minimizing storage requirements and enhancing parallel processing speed. Experimental results demonstrate that, for a 32×256×8 MIMO downlink precoding task with 90% sparsity, the symbol error rate is reduced to 0.1% at a signal-to-noise ratio of 20dB, achieving 8.35× reduction in storage overhead, 39.4× power saving and 9.85× speedup. These results position our accelerator as a promising candidate for processing sparse data in 5G massive MIMO systems.
KW - Adaptive mapping matching
KW - CIM
KW - Gaussian algorithm
KW - Massive MIMO
KW - Multi-sparse mode
UR - https://www.scopus.com/pages/publications/105029351135
U2 - 10.1109/ICCAD66269.2025.11240949
DO - 10.1109/ICCAD66269.2025.11240949
M3 - 会议稿件
AN - SCOPUS:105029351135
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
BT - 2025 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2025 - Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 44th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2025
Y2 - 26 October 2025 through 30 October 2025
ER -