TY - GEN
T1 - An adaptive fault detection threshold hardware circuit design to reduce False Alarms
AU - Cui, Y.
AU - Shi, J.
AU - Chen, L.
AU - Liu, K.
AU - An, W.
PY - 2015
Y1 - 2015
N2 - Built-In Tests (BITs), responsible for detecting and isolating faults, are widely used in mechanical and electronic products to improve reliability and testability. However, the False Alarm (FA) phenomenon greatly reduces the BIT accuracy and credibility, which becomes one of the most troublesome problem in BIT applications. Compared with the single-threshold fault detection method, an adaptive and automatically adjustable threshold for determining the current state would better to reduce false alarms. In this paper, an adaptive fault detection threshold hardware circuit is designed and tested. The concept of the adaptive fault detection threshold strategy is introduced at the beginning. The outlines and details of circuit design implementations are also discussed, including the function requirements, input/output specifications, and implementation tools. Finally, a hardware BIT circuit board monitoring a typical fault mode is made out, and a performance analysis of the hardware design is carried out.
AB - Built-In Tests (BITs), responsible for detecting and isolating faults, are widely used in mechanical and electronic products to improve reliability and testability. However, the False Alarm (FA) phenomenon greatly reduces the BIT accuracy and credibility, which becomes one of the most troublesome problem in BIT applications. Compared with the single-threshold fault detection method, an adaptive and automatically adjustable threshold for determining the current state would better to reduce false alarms. In this paper, an adaptive fault detection threshold hardware circuit is designed and tested. The concept of the adaptive fault detection threshold strategy is introduced at the beginning. The outlines and details of circuit design implementations are also discussed, including the function requirements, input/output specifications, and implementation tools. Finally, a hardware BIT circuit board monitoring a typical fault mode is made out, and a performance analysis of the hardware design is carried out.
UR - https://www.scopus.com/pages/publications/84906691654
U2 - 10.1201/b17399-123
DO - 10.1201/b17399-123
M3 - 会议稿件
AN - SCOPUS:84906691654
SN - 9781138026810
T3 - Safety and Reliability: Methodology and Applications - Proceedings of the European Safety and Reliability Conference, ESREL 2014
SP - 867
EP - 872
BT - Safety and Reliability
PB - CRC Press/Balkema
T2 - European Safety and Reliability Conference, ESREL 2014
Y2 - 14 September 2014 through 18 September 2014
ER -