A Timing-driven Analytical Placer for Gate-Level Partitioned Monolithic 3D ICs

With the prevalence of data intensive applications like neuromorphic computing and big data processing, monolithic 3D (M3D) integration is proposed recently to provide ultrahigh memory bandwidth and can effectively improve the area, performance and power consumption of the chip. In this paper, we observe that it is essential to co-optimize the wirelength and critical path timing in placement for gate-level partitioned M3D ICs, which can take full advantage of dense MIVs and achieve better timing performance. Therefore, we propose a timing-driven analytical placement workflow for monolithic 3D ICs. Guided by timing analysis, the timing critical paths are selected and divided onto different tiers to exploit short vertical interconnects for timing optimization. Experimental results show that compared to TSV based 3D ICs, our timing-driven analytical placer for M3D ICs can reduce the chip footprint, the half-perimeter wirelength (HPWL) and the circuit delay by 70.2%, 55.6%, and 49.6% respectively.