A Survey of Architecture Design and Optimization for NVM-Based Cache Hierarchy and Network-on-Chip

With the emergence of artificial intelligence and big data computing, “memory wall” problem is becoming more prominent and a roadblock for performance improvement. On-chip cache hierarchy and NoC play big roles to break “memory wall”. However, large data storage capacity and high data bandwidth cannot be met easily by conventional memory techniques such as SRAM due to the high leakage power and large area overhead. To deal with these problems, applying emerging nonvolatile memory (NVM) for on-chip cache and NoC is a promising approach. This paper reviews optimization schemes for NVM-based on-chip cache hierarchy and NoC router. We categorize the schemes according to their optimization objectives to highlight their strengths and weaknesses in the context of motivating background. We expect that this survey may help researchers get deeper insights into the potential of applying NVM in next generation high performance computing systems.