@inproceedings{17500b50dd31482e802333e66e4acbd9,
title = "A Sub-Sampling Fast Lock Detector for Fractional-N PLL",
abstract = "In this paper, a sub-sampling lock detector is proposed to detect the lock or out-of-lock state for fractional-N phase-locked loop (PLL) in various applications, such as the generation of Frequency-Modulated Continuous Wave (FMCW) signal or controlling the loop switching of sub-sampling PLL (SSPLL). The proposed lock detector is designed without powerconsuming analog comparator or switched-capacitor circuits. The proposed detector can detect the lock and out-of-lock state within less than 20 reference clock periods and the total consumption is only 290uW with 80 MHz reference clock in a 40-nm CMOS technology.",
keywords = "CMOS, Lock Detection, PLL, Sub-Sampling",
author = "Fanxun Cai and Ziyang Li and Zijie Wang and Yunqi Yang and Pengcheng Wang and Yilin Xu and Lianbo Wu and Hui Zhang",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025 ; Conference date: 12-10-2025 Through 15-10-2025",
year = "2025",
doi = "10.1109/APCCAS67402.2025.11379857",
language = "英语",
series = "Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025",
address = "美国",
}