A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation

Hamming code is a linear error correcting code that is widely used in memory and communication systems. In general, a codec hardware is required to encode or decode the information. In this brief, we propose for the first time a spintronic in-memory computing (IMC) network consisting of magnetic tunnel junctions (MTJs) for Hamming codec hardware implementation. Such an IMC network stores the generation matrix or parity-check matrix in a spin transfer torque (STT) MTJ array and performs vector matrix multiplication (VMM) with modulo-2 to generate desired codewords or syndrome-vectors during the encoding or decoding process, respectively. The output results are represented by the states of the spin orbit torque (SOT) MTJs, which can unipolarly flip based on the modulo-2 VMM results. Based on our developed physics-based STT and SOT MTJ SPICE models, we verified the functionality and evaluated the performance of the design in the 40nm technology node. The simulation results show that our work can generate codewords and syndrome-vectors with much lower (103-105 times) energy consumption compared to state-of-the-art designs based on memristor network, CPU and GPU.